Formal Modeling of Shared Resources in Many-core Platforms for Interference Analysis H/F

Description: Job descriptionSafety-critical systems such as autonomous vehicles and modern avionic computers have to satisfy strong timing requirements. A failure to meet a timing constraint, missing a deadline for example, may result in serious malfunctions. Therefore, it is crucial to compute safe timing bounds for these systems.A conventional timing analysis approach is the Worst-Case Execution Time (WCET), which aims at statically finding a safe and tight bound on the worst possible execution time of a task running on a given architecture . Thus, both the software (program flow information) and the hardware (architectural features like the pipeline and caches) are essential in verifying the timing behavior of the aforementioned critical systems.From a software perspective, when multi-threaded safety-critical applications are deployed on many-core architectures, they may cause interference delays due to the concurrent accesses to shared hardware resources like RAM, caches, buffers, interconnect, etc. Thus, the software behavior contributes a large part of the interference delays and should be analyzed while taking into account the timing model of the underlying hardware.From a hardware point of view, modern many-core architectures integrate multiple processing units enabling high computational capabilities when executing parallel workloads. These many-corearchitectures like Kalray's third generation many-core processor MPPA Coolidge, the Celerity RISC-V tiered accelerator and OpenPiton+Ariane RISC-V many-core feature common performance enhancing components like the pipeline and caches as well as advanced acceleration and speculation mechanisms. For instance, Kalray MPPA includes pipeline acceleration mechanisms, namely, a prefetch buffer and a write buffer. These mechanisms influence significantly the timing behavior of the hardware. Hence, analyzing their timing behavior is necessary to ensure an accurate WCET estimate.The focus of this internship is to propose formal models of hardware resources for the purpose of bounding interference delays. More precisely, we aim at capturing the timing behavior of two performance enhancing micro-architectural components, which are the data cache and the write buffer.These formal models will be integrated within an in-house verification framework called Fik. Fik is based on formal executable semantics of the instruction set architecture (ISA) of MPPA Coolidge and formal memory and pipeline models. Enhanced with the data cache and write buffer models, Fik will be able to generate timed execution traces that we will analyze in order to characterize interference delays.A funded PhD position is available on this subject after this internship. Applicant Profile Computer engineering student (final year) or master2 student- Background in computer architecture- Background in concurrent and parallel programming- Background in compilation techniquesPosition location SiteSaclay Job locationFrance, Ile-de-France, Essonne (91) Location PalaiseauCandidate criteria Prepared diploma Bac+5 - Master 2 PhD opportunityOuiRequester Position start date01/03/2022 General information Organisation The French Alternative Energies and Atomic Energy Commission (CEA) is a key player in research, development and innovation in four main areas :? defence and security,? nuclear energy (fission and fusion),? technological research for industry,? fundamental research in the physical sciences and life sciences. Drawing on its widely acknowledged expertise, and thanks to its 16000 technicians, engineers, researchers and staff, the CEA actively participates in collaborative projects with a large number of academic and industrial partners. The CEA is established in ten centers spread throughout France Reference 2021-19338